1. Technical Field
The present disclosure relates to a nonvolatile memory device. In more detail, the present disclosure relates to a resistance change-type nonvolatile memory device.
2. Description of the Related Art
With resent development in digital technology, electronic apparatuses such as a portable information technology device, an information technology home appliance, etc. have been further improved in performance. Therefore, there are increasing demands for increasing the capacity, decreasing the write electric power, increasing the write/read speed, and increasing the life time of a nonvolatile memory device.
For these demands, miniaturization of a flash memory using an existing floating gate is advanced. On the other hand, development of a nonvolatile memory device (resistance change-type memory) using a resistance-change element in which a resistance value is reversibly changed by applying a voltage pulse is also advanced. This resistance change-type memory includes a memory cell which can be configured in a simple structure and is thus expected to be further miniaturized, increased in speed, and decreased in power consumption.
A memory cell which performs a memory operation has been configured by using one transistor and one memory element. Hereinafter, this memory cell may be referred to as a “1T1 R-type memory cell”. Higher integration has been achieved by this memory cell.
International Publication No. 2009/008080 discloses a semiconductor device using a 1T1R-type memory cell. The semiconductor device has a configuration in which a bit line BL connected to an upper electrode of a resistance-change element crosses at a right angle a source line SL to which a lower electrode of the resistance-change element is connected through a transistor (FIG. 2 of International Publication No. 2009/008080). In the memory device, a resistance change-type element RM is connected to a n-type semiconductor region (source/drain) through a plurality of plugs and first layer wiring which extend in a vertical direction (a region z2 in FIG. 7 of International Publication No. 2009/008080).
Japanese Unexamined Patent Application Publication No. 2004-355670 discloses a nonvolatile memory device using a 1T1R-type memory cell. The memory has a configuration in which a bit line connected to one of the electrodes of a memory element and a common source line connected to the other electrode of the memory element extend in parallel (FIG. 4 of Japanese Unexamined Patent Application Publication No. 2004-355670).
A usual nonvolatile memory device has a problem that by arranging in parallel a bit line BL (wiring connected to a nonvolatile memory device) and a source line SL (wiring connected to one of the main terminals of a transistor), power consumption of writing in a selected memory element is desired to be decreased, the size of a memory cell is desired to be further decreased with a higher operation speed, or an operation is desired to be stabilized by decreasing wiring delay.